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MB84VB2000 Datasheet(PDF) 13 Page - fujitsu semiconductor |
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MB84VB2000 Datasheet(HTML) 13 Page - fujitsu semiconductor |
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13 / 28 page  13 MB84VB2000-10/MB84VB2001-10 s AC CHARACTERISTICS •CE Timing • Read Only Operations Characteristics Note: Test Conditions–Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V Parameter Symbols Description Test Setup -10 Unit JEDEC Standard —tCCR CE Recover Time — Min. 0 ns Parameter Symbols Description Test Setup -10 (Note) Unit JEDEC Standard Min. Max. tAVAV tRC Read Cycle Time — 100 — ns tAVQV tACC Address to Output Delay CE = VIL OE = VIL —100 ns tELQV tCE Chip Enable to Output Delay OE = VIL —100 ns tGLQV tOE Output Enable to Output Delay — — 40 ns tEHQZ tDF Chip Enable to Output High-Z — — 30 ns tGHQZ tDF Output Enable to Output High-Z — — 30 ns tAXQX tOH Output Hold Time from Addresses, CE or OE, Whichever Occurs First —0 — ns —tREADY RESET Pin Low to Read Mode — — 20 µs — tELFL tELFH CE or BYTE Switching Low or High — — 5 ns |
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