TSB41AB1PHP datasheet(29/71 Pages) TI1

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TSB41AB1

IEEE 1394a2000 ONEPORT CABLE

TRANSCEIVER/ARBITER

SLLS423I − JUNE 2000 − REVISED MARCH 2005

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

APPLICATION INFORMATION

component connection (continued)

Outer Shield Termination

Chassis GND

Figure 12. Nonisolated Outer Shield Termination

LPS

10 k

Ω

10 k

Ω

Link Power

Square Wave Input

Figure 13. Nonisolated Circuit Connection Variations for LPS

LPS

13.7 k

Ω

Square Wave Signal

10 k

Ω

PHY VDD

0.033

µF

PHY GND

NOTE: As long as the resistance ratio is maintained between 1.61:1 and

1.33:1, any values of resistors may be used.

Figure 14. Isolated Circuit Connection for LPS

crystal selection

The TSB41AB1 and other TI PHY devices are designed to use an external 24.576-MHz crystal connected

between the XI and XO terminals to provide the reference for an internal oscillator circuit. This oscillator in turn

drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data

at the S100 through S400 media data rates.

A variation of less than

±100 ppm from nominal for the media data rates is required by IEEE Std 1394-1995.

Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and

PHYs must be able to compensate for this difference over the maximum packet length. Larger clock variations

may cause resynchronization overflows or underflows, resulting in corrupted packet data.

For the TSB41AB1, the SYSCLK output may be used to measure the frequency accuracy and stability of the

internal oscillator and PLL from which it is derived. The frequency of the SYSCLK output must be within

±100 ppm of the nominal frequency of 49.152 MHz.

TSB41AB1PHP Datasheet(PDF) 29 Page - Texas Instruments

TSB41AB1PHP Datasheet(HTML) 29 Page - Texas Instruments

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