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AS5047D Datasheet(PDF) 11 Page - ams AG |
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AS5047D Datasheet(HTML) 11 Page - ams AG |
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11 / 37 page  ams Datasheet: 2014-Jun-27 [v1-02] AS5047D – 11 Detaile d Desc rip t ion SPI Timing The AS5047D SPI timing is shown in Figure 11. Figure 11: SPI Timing Diagram Figure 12: SPI Timing Parameter Description Min Max Units tL Time between CSn falling edge and CLK rising edge 350 ns tclk Serial clock period 100 ns tclkL Low period of serial clock 50 ns tclkH High period of serial clock 50 ns tH Time between last falling edge of CLK and rising edge of CSn tclk / 2 ns tCSn High time of CSn between two transmissions 350 ns tMOSI Data input valid to falling clock edge 20 ns tMISO CLK edge to data output valid 20 ns tOZ Release bus time after CS rising edge. 10 ns CSn (Input) CLK (Input) MOSI (Input) MISO (Output) tclk tL tMOSI tMISO tOZ tOZ tH tCSn tclkL tclkH Data[15] Data[15] Data[14] Data[14] Data[0] Data[0] |
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