7-85

HPMX-3003 Pin Description Table

No. Mnemonic

Description

Typical Signal

Description

1

Gnd

ground

0 V

Short path with minimal parasitics. Ground pins are

2

Gnd

ground

0 V

also the primary thermal path for heatsinking the device.

3

Gnd

ground

0 V

input to Power

DC: -0.75 V

Bias through 500

Ω resistor and 100 pF capacitor. 50 Ω trans-

Amplifier

RF: +4 dBm

mission line with DC blocking capacitor (>24 pF) to input.

Shunt 2.7 pF used on test board to match input at 1.9 GHz.

5

Gnd

ground

0 V

Short path with minimal parasitics. Ground pins are also

6

Gnd

ground

0 V

the primary thermal path for heatsinking the device.

7

VD1

Drain bias

+3 V, 100 mA

Set drain bias to 3 V (can be tied to same rail as PA out).

of PA stage 1

Bypass with 100 pF capacitor at pin.

8

LNA out

output of LNA

DC: +3 V, 5 mA

Bias through 5 nH choke (printed on PC board) and 100 pF

RF: -7 dBm

bypass capacitor to 10

Ω resistor and 1000 pF bypass

capacitor. Can be operated from 3 to 5 V supply line. 50

Ω

transmission line with DC block (>24 pF) to receiver.

9

Gnd

ground

0 V

Short path with minimal parasitics. Ground pins are also

10

Gnd

ground

0 V

the primary thermal path for heatsinking the device.

11

LNA in

input of LNA

DC: 0 V

50

Ω transmission line from switch. Input blocking capacitor

RF: -20 dBm

(24 pF) and shunt 5 nH inductor to ground (noise match at

1.9 GHz) required. Typically a filter is employed between the

LNA input and the switch.

12

Gnd

ground

0 V

Short path with minimal parasitics. Ground pins are also

the primary thermal path for heatsinking the device.

13

SW1

switch

DC: 0 V

Switch input or output. Symmetrical with SW2. 50

Ω

terminal 1

RF: -20 dBm

transmission line to LNA (or PA). Line should not carry

DC voltage.

14

C1

switch control 1

closed: 0 V

High impedance line to control switch, used in conjunction

open: -3 to -5 V

with C2. C2 should be open when C1 is closed.

15

Antenna

switch center

DC: 0 V

50

Ω transmisson line to/from antenna. Line should not

pole

RF: +26 dBm

carry DC voltage.

16

C2

switch control 2

closed: 0 V

High impedance line to control switch, used in conjunction

open: -3 to -5 V

with C1. C1 should be open when C2 is closed.

17

Gnd

ground

0 V

Short path with minimal parasitics. Ground pins are also the

primary thermal path for heatsinking the device.

18

SW2

switch

DC: 0 V

Switch input or output. Symmetrical with SW1. 50

Ω

terminal 2

RF: +4 dBm

transmission line to PA (or LNA). Line should not carry

DC voltage.

19

Gnd

ground

0 V

Short path with minimal parasitics. Ground pins are also

20

Gnd

ground

0 V

the primary thermal path for heatsinking the device.

21

PA out

output of PA

DC: 3 V, 350 mA

2.7 pF chip capacitor to ground provides 1.9 GHz output

22

PA out

output of PA

RF: +27 dBm

match for PA. 50

Ω transmission line to switch. LC choke

and blocking C used. Typically a filter is employed between

the PA output and the switch input.

23

Gnd

ground

0 V

Short path with minimal parasitics. Ground pins are also

24

Gnd

ground

0 V

the primary thermal path for heatsinking the device.

25

PA out

output of PA

DC: 3 V, 350 mA

Leave unconnected; use pins 21 & 22 for PA out.

RF: +27 dBm

26

Gnd

ground

0 V

Short path with minimal parasitics. Ground pins are also

the primary thermal path for heatsinking the device.

27

VG2

Gate bias on

-0.75 V

Provide bias through 10

Ω resistor. Bypass to ground at pin

PA stage 2

with 10 pF capacitor, and on power supply side of resistor

with 1000 pF capacitor.

28

Gnd

ground

0V

Short path with minimal parasitics. Ground pins are also the

primary thermal path for heatsinking the device.