PCF8534A datasheet(8/52 Pages) NXP

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PCF8534A

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Product data sheet

Rev. 6 — 25 July 2011

8 of 52

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

The host microcontroller maintains the 2-line I2C-bus communication channel with the

PCF8534A.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to VSS. The only other connections required to complete the system are the

power supplies (pins VDD, VSS, and VLCD) and the LCD panel selected for the application.

7.1 Power-On Reset (POR)

At power-on the PCF8534A resets to the following starting conditions:

• All backplane and segment outputs are set to VLCD

• The selected drive mode is: 1:4 multiplex with 1⁄3 bias

• Blinking is switched off

• Input and output bank selectors are reset

• The I2C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• Display is disabled

Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow

the reset action to complete.

7.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of

three impedances connected in series between VLCD and VSS. If the 1⁄2 bias voltage level

for the 1:2 multiplex drive mode configuration is selected, the center impedance is

bypassed by switch. The LCD voltage can be temperature compensated externally, using

the supply to pin VLCD.

Fig 5.

Typical system configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

2Cb

SDA

SCL

OSC

60 segment drives

4 backplanes

LCD PANEL

(up to 240

elements)

PCF8534A

SA0

VDD

VSS

VDD

VLCD

001aah616

≤

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