ICS650-14B

Networking System Clock

MDS 650-14B A

1

Revision 082800

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com

PRELIMINARY INFORMATION

The ICS650-14B is a low cost, low jitter, high

performance clock synthesizer customized for

networking systems applications. Using analog

Phase-Locked Loop (PLL) techniques, the device

accepts a 25.0 MHz clock or fundamental mode

crystal input to produce multiple output clocks of

one fixed 25.0 MHz, a four (plus one) frequency

selectable bank, and two frequency selectable

clocks. All output clocks are frequency locked

together. The ICS650R-14B outputs

all have 0 ppm synthesis error.

Block Diagram

Description

Features

• Packaged in 20 pin (150 mil) SSOP (QSOP)

• 25.00 MHz fundamental crystal or clock input

• One fixed output clock of one 25.0 MHz

• One bank of four frequency selectable

output clocks

• Three frequency selectable clock outputs

• Zero ppm synthesis error in all clocks

• Ideal for networking systems

• Full CMOS output swing

• Advanced, low power, sub-micron CMOS process

• 3.0V to 5.5V operating voltage

• Industrial temperature range available

Clock

Buffer/

Crystal

Oscillator

VDD

GND

Clock Synthesis

and Control

Circuitry

25.00 MHz

crystal or clock

25.00 MHz

2

2

Output

Buffer

CLKA5

Output

Buffer

X1/ICLK

X2

CLKB

Output

Buffer

Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).

OE (All outputs)

Output

Buffer

CLKA 1:4

4

SELA 0:1

2

SELB 0:1

2

SELC

CLKC

Output

Buffer