4

ICS9147-14

Electrical Characteristics at 3.3V

Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.

AC Characteristics

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Rise Time

1

20pF load, 0.8 to 2.0V

CPU, IOAPIC, Fixed & REF

-0.9

1.5

ns

Fall Time

1

20pF load, 2.0 to 0.8V

CPU, IOAPIC, Fixed & REF

-0.8

1.4

ns

Rise Time

1

20pF load, 20% to 80%

CPU, IOAPIC, Fixed & REF

-1.5

2.5

ns

Fall Time

1

20pF load, 80% to 20%

CPU, IOAPIC, Fixed& REF

-1.4

2.4

ns

Rise Time

1

20pF load, 0.8 to 2.0V PCI, SDRAM

-

0.9

1.5

ns

Fall Time

1

20pF load, 2.0 to 0.8V PCI, SDRAM

-

0.8

1.4

ns

Rise Time

1

20pF load, 0.4 to 2.0V , CPU and

IOAPIC with VDDL = 2.5V

--

3.0

ns

20pF load, 2.0 to 0.4V, CPU and

IOAPIC with VDDL = 2.5V

--

2.0

ns

Duty Cycle

1

20pF load @ VOUT=1.4V

All clocks except REF

45

50

55

%

Duty Cycle

1

20pF load @ VOUT=1.4V

REF outputs

40

50

60

%

Jitter, One Sigma

1

CPU & PCICLK Clocks; Load=20pF,

SDRAM; Load = 30pF

-

50

150

ps

Jitter, Absolute

1

CPU & PCICLK Clocks; Load=20pF,

SDRAM; Load = 30pF

-250

-

250

ps

Jitter, Cycle to Cycle

CPU

-

200

350

ps

Jitter, One Sigma

1

Fixed CLK; Load=20pF

-

1

3

%

Fixed CLK; Load=20pF

-5

2

5

%

12.0

14.318

16.0

MHz

Logic Input Capacitance

1

Logic input pins

-

5

-

pF

Crystal Oscillator Capacitance

1

X1, X2 pins

-

18

-

pF

Power-on Time

1

From VDD=1.6V to 1st crossing of

66.6 MHz VDD supply ramp < 40ms

-2.5

4.5

ms

Clock Skew

1

CPU to CPU or PCI to PCI;

Load=20pF; @1.4V (Same VDD)

-

150

250

ps

Clock Skew

1

SDRAM to SDRAM;

Load=20pF; @1.4V

-

300

500

ps

Clock Skew

1

CPU to PCICLK; Load=20pF; @1.4V

(CPU is early)

1

2.1

4

ns