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ICS9147F-14 Datasheet(PDF) 1 Page - Integrated Circuit Systems

Part # ICS9147F-14
Description  Frequency Generator & Integrated Buffers for PENTIUM/ProTM
PDF  7 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9147F-14 Datasheet(HTML) 1 Page - Integrated Circuit Systems

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Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9147-14
Block Diagram
Pentium is a trademark of Intel Corporation
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
9147-14 Rev B 071897P
•
Four copies of CPU clock
•
Twelve SDRAM (3.3VTTL), usable asAGP clocks
•
Seven copies of PCICLK clock (synchronous with CPU
clock/2 or CPU/2.5 for 75 and 83.3 MHz CPU)
•
CPU clocks to PCICLK clocks skew 1-4ns, center 2.6ns.
•
OneIOAPICclock@14.31818MHz
•
Two copies of Ref. clock @14.31818MHz
•
Ref. 14.31818MHz Xtal oscillator input
•
SeparateVDDL1 for four CPU and single IOAPIC output
buffers to allow 2.5V output (or Std. Vdd)
•
One each 48/ 24MHz (3.3V TTL)
•
3.3Voutputs: SDRAM, PCI, REF, 48/24MHz.
•
2.5V or 3.3V outputs: CPU, IOAPIC.
•
20 ohm CPU clock output impedance
•
20 ohm PCI clock output impedance
•
1.5ns rise time (30 pF loading)
•
±250 ps CPU, PCI clock skew
•
350ps (cycle by cycle) CPU jitter
•
2ms Power up clock stable time
•
45-55% Clock duty cycle
•
48 pin 300 mil SSOP package
•
3.0V – 3.7V supply range w/2.5V compatible outputs
The ICS9147-14 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro.Two bidirectional I/O pins (FS1,FS2) are latched
at power-on to the functionality table, with FS0 selectable in
real-time to toggle between conditions.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPU outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining50±5% duty cycle. The REF clock outputs
typically provide better than 0.5V/ns slew rates. Seperate
buffers supply pins VDDL1 allow for 3.3V or reduced voltage
swing (from 2.9 to 2.5V) for CPU (0:3) and IOAPIC outputs.
Pin Configuration
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2, 24MHz, 48MHz
VDD2 = PCICLKF, PCICLK(0:5)
VDD3 = SDRAM (0;11)
VDDL1 = CPUCLK (0:3)
* Internal Pull-up Resistor of
300K to 3.3V on indicated inputs
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.


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