2

ICS9250-09

Pin Descriptions

Pin number

Pin name

Type

Description

1

GNDREF

PWR

Gnd pin for REF clocks

2, 3

REF(0:1)

OUT

14.318MHz reference clock outputs at 3.3V

4

VDDREF

PWR

Power pin for REF clocks

5

X1

IN

XTAL_IN 14.318MHz crystal input

6

X2

OUT

XTAL_OUT Crystal output

7, 13, 19

GNDPCI

PWR

Gnd pin for PCICLKs

8

PCICLK_F

OUT

Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected

by the PCI_STOP# input.

9, 11, 12, 14, 15,

17, 18

PCICLK[1:7]

OUT

PCI clock outputs at 3.3V. Synchronous to CPU clocks.

10, 16

VDDPCI

PWR

3.3Volts power pin for PCICLKs

20, 24

GND66

PWR

Gnd pin for 3V66 outputs

21, 22, 25, 26

3V66[0:3]

OUT

66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is

driven active..

23, 27

VDD66

PWR

power pin for the 3V66 clocks.

28

SEL 133/100#

IN

This selects the frequency for the CPU and CPU/2 outputs. High =

133MHz, Low=100MHz

29

GND48

PWR

Ground pin for the 48MHz output

30

48MHz

OUT

Fixed 48MHz clock output. 3.3V

31

VDD48

PWR

Power pin for the 48MHz output.

32, 33

SEL[0:1]

IN

Function select pins. See truth table for details.

34

SPREAD#

IN

Enables spread spectrum when active(Low). modulates all the CPU, PCI,

IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and 48MHz

clocks. 0.5% down spread modulation.

35

PD#

IN

This asynchronous input powers down the chip when drive active(Low).

The internal PLLs are disabled and all the output clocks are held at a Low

state.

36

CPU_STOP#

IN

This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at

logic "0" when driven active(Low). Does not affect the CPU/2 clocks.

37

PCI_STOP#

IN

This asynchronous input halts the PCICLK[1:7] at logic"0" when driven

active(Low). PCICLK_F is not affected by this input.

38

GNDCOR

PWR

Ground pin for the PLL core

39

VDDCOR

PWR

Power pin for the PLL core. 3.3V

43, 47

VDDLCPU

PWR

Power pin for the CPUCLKs. 2.5V

40, 44

GNDLCPU

PWR

Ground pin for the CPUCLKs

41, 42, 45, 46

CPUCLK[0:3]

OUT

Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state

of the SEL 133/100MHz.

48

GNDLCPU/2

PWR

Ground pin for the CPU/2 clocks.

49, 50

CPU/2[0:1]

OUT

2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz depending on

the state of the SEL 133/100# input pin.

51

VDDLCPU/2

PWR

Power pin for the CPU/2 clocks. 2.5V

52

GNDLIOAPIC

PWR

Ground pin for the IOAPIC outputs.

53, 54, 55

IOAPIC[0:2]

OUT

IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at

16.67MHz.

56

VDDLIOAPIC

PWR

Power pin for the IOAPIC outputs. 2.5V.