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ICS9250-09 Datasheet(PDF) 3 Page - Integrated Circuit Systems

Part # ICS9250-09
Description  Frequency Timing Generator for PENTIUM II Systems
PDF  12 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS9250-09 Datasheet(HTML) 3 Page - Integrated Circuit Systems

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3
ICS9250-09
Frequency Select:
Note:
1. TCLK is a test clock driven on the x1 input during test mode.
#
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Power Management Features:
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
4.All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW.
5. CPU/2, IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions
except PD# = LOW
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