28F008B3 datasheet(5/49 Pages) INTEL

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SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE

PRELIMINARY

1.0

INTRODUCTION

This

preliminary

datasheet

contains

the

specifications for the Advanced Boot Block flash

memory family, which is optimized for low power,

portable systems. This family of products features

1.8V–2.2V or 2.V–3.6V I/Os and a low VCC/VPP

operating range of 2.7V–3.6V

for read and

program/erase operations. In addition this family is

capable of fast programming at 12V. Throughout

this document, the term “2.7V” refers to the full

voltage range 2.7V–3.6V (except where noted

otherwise) and “VPP = 12V” refers to 12V ±5%.

Section 1 and 2 provides an overview of the flash

memory family including applications, pinouts and

pin descriptions. Section 3 describes the memory

organization and operation for these products.

Finally, Sections 4, 5, 6 and 7 contain the

operating specifications.

1.1

Smart 3 Advanced Boot Block

Flash Memory Enhancements

The new 8-Mbit and 16-Mbit Smart 3 Advanced

Boot Block flash memory provides a convenient

upgrade from and/or compatibility to previous 4-

Mbit and 8-Mbit Boot Block products. The Smart 3

product functions are similar to lower density

products in both command sets and operation,

providing similar pinouts to ease density upgrades.

The Smart 3 Advanced Boot Block flash memory

features

• Enhanced blocking for easy segmentation of

code and data or additional design flexibility

• Program Suspend command which permits

program suspend to read

• WP# pin to lock and unlock the upper two (or

lower two, depending on location) 8-Kbyte

blocks

• VCCQ input for 1.8V–2.2V on all I/Os. See

Figures 1–3 for pinout diagrams and VCCQ

location

• Maximum program time specification for

improved data storage.

Table 1. Smart 3 Advanced Boot Block Feature Summary

Feature

28F016B3/28F008B3/28F004B3

Reference

VCC Read Voltage

2.7V– 3.6V

Table 9, Table 12

VCCQ I/O Voltage

1.8V–2.2V or 2.7V– 3.6V

Table 9, Table 12

VPP Program/Erase Voltage

2.7V– 3.6V or 11.4V– 12.6V

Table 9, Table 12

Bus Width

8 bits

Table 2

Speed

120 ns

Table 15

Memory Arrangement

1 Mbit x 8 (8 Mbit), 2 Mbit x 8 (16 Mbit)

Blocking (top or bottom)

Eight 8-Kbyte parameter blocks (8/16 Mbit) &

Fifteen 64-Kbyte blocks (8 Mbit)

Thirty-one 64-Kbyte main blocks (16 Mbit)

Section 2.2

Figures 4 and 5

Locking

WP# locks/unlocks parameter blocks

All other blocks protected using VPP switch

Section 3.3

Table 8

Operating Temperature

Extended: –40

°C to +85°C

Table 9, Table 12

Program/Erase Cycling

10,000 cycles

Table 9, Table 12

Packages

40-Lead TSOP, 48-Ball

µBGA* CSP

Figures 1, 2, and 3

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