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80960HA Datasheet(PDF) 57 Page - Intel Corporation |
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80960HA Datasheet(HTML) 57 Page - Intel Corporation |
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57 / 102 page ![]() 80960HA/HD/HT Advance Information Datasheet 51 Figure 34. Non-Burst, Non-Pipelined Write Request with Wait States ADS A31:2, W/R BLAST DT/R DEN WAIT D31:0, CLKIN A3 2 1 D 1 Out A Valid Valid BE3:0 DP3:0 PCHK Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 Disabled 0 OFF 0 1 0001 X xx X x Enabled 1 X xxxxx 3 00011 X xx Disabled 0 X xxxxx Function Bit Value External Ready Control Pipe- Lining Parity Enable NRAD NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. PMCON D/C,SUP, LOCK,CT3:0 |
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