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80960HA Datasheet(PDF) 59 Page - Intel Corporation |
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80960HA Datasheet(HTML) 59 Page - Intel Corporation |
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59 / 102 page ![]() 80960HA/HD/HT Advance Information Datasheet 53 Figure 36. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus ADS A31:4, SUP, CT3:0, D/C, BE3:0,LOCK W/R BLAST DT/R DEN A3:2 WAIT D31:0, CLKIN A2 1 D 1 D 1 D 1 D 1 A In1 In2 In3 In0 Valid 00 11 01 10 DP3:0 PCHK Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 Enabled 1 OFF 0 1 0001 32-Bit 10 X x Enabled 1 X xx X xxxxx 1 01 Disabled 0 2 00010 Function Bit Value External Ready Control Pipe- Lining Parity Enable NRAD NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. PMCON |
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