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80960JD Datasheet(PDF) 46 Page - Intel Corporation |
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80960JD Datasheet(HTML) 46 Page - Intel Corporation |
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46 / 61 page  42 PRELIMINARY 80960JD 5.0 BUS FUNCTIONAL WAVEFORMS Figures 25 through 30 illustrate typical 80960JD bus transactions. Figure 31 depicts the bus arbitration sequence. Figure 32 illustrates the processor reset sequence from the time power is applied to the device. Figure 33 illustrates the processor reset sequence when the processor is in operation. Figure 34 illustrates the processor ONCE sequence from the time power is applied to the device. Figures 35 and 36 also show accesses on 32-bit buses. Tables 19 through 22 summarize all possible combinations of bus accesses across 8-, 16-, and 32-bit buses according to data alignment. Figure 25. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus CLKIN AD31:0 ALE ADS A3:2 BE3:0 WIDTH1:0 D/C W/R DT/R DEN RDYRCV BLAST ADDR D In Invalid ADDR DATA Out 10 10 Ta Td Tr Ti T i Ta Td Tr T i Ti F_JF030A |
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