82C50 datasheet(21/21 Pages) INTERSIL

Part #	82C50

Description	CMOS Asynchronous Communications Element

PDF	21 Pages

Scroll/Zoom	100%

Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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FIGURE 8. RECEIVER TIMING

FIGURE 9. TRANSMITTER TIMING

FIGURE 10. MODEM CONTROLS TIMING

Timing Waveforms (Continued)

tSCD (34)

8 CLKS

RCLK

SAMPLE CLK

SIN (RECEIVER INPUT DATA)

SAMPLE CLK

INTERRUPT

(DATA READY OR RCVR ERR)

DISTR/DISTR

(READ REC DATA BUFFER OR ROLSR)

NOTE 2

START

DATA BITS (5-8)

PARITY

STOP

tSINT (35)

tRINT

(36)

ACTIVE

NOTES:

1. See Write Cycle Timing.

2. See Read Cycle Timing.

NOTES:

1. See Write Cycle Timing.

2. See Read Cycle Timing.

START

DATA (5-8)

PARITY

STOP

(1-2)

START

tSTI (40)

tIR (41)

SERIAL OUT

(SOUT)

INTERRUPT

(THRE)

DOSTR/DOSTR

(WR THR)

NOTE 1

DISTR/DISTR

(RD IIR)

NOTE 2

(38)

tIRS

(39)

tSI

(37)

tHR

(37)

tHR

ACTIVE

tMDO

(42)

tMDO

(42)

tRIM

(44)

(43) tSIM

tSIM

(43)

tSIM

(43)

DOSTR/DOSTR (WR MCR)

NOTE 1

RTS, DTR

OUT1, OUT2

CTS, DST, DCD

INTERRUPT

DISTR/DISTR (RD MSR)

NOTE 2

ACTIVE

tRIM

(44)

NOTES:

1. See Write Cycle Timing.

2. See Read Cycle Timing.

82C50A

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