4-284

SYMBOL

PARAMETER

LIMITS

UNITS

TEST CONDITIONS

MIN

MAX

(1) TlVOV

Propagation Delay Input to Output

5

25

ns

See Notes 2, 3

(2) TSHOV

Propagation Delay STB to Output

10

50

ns

See Notes 2, 3

(3) TEHOZ

Output Disable Time

5

22

ns

See Notes 2, 3

(4) TELOV

Output Enable Time

10

45

ns

See Notes 2, 3

(5) TlVSL

Input to STB Set Up Time

0

-

ns

See Notes 2, 3

(6) TSLIX

Input to STB Hold Time

30

-

ns

See Notes 2, 3

(7) TSHSL

STB High Time

15

-

ns

See Notes 2, 3

(8) TR, TF

Input Rise/Fall Times

-

20

ns

See Notes 2, 3

NOTES:

1. Output load capacitance is rated 300pF for both ceramic and plastic packages.

2. All AC Parameters tested as per test load circuits. Input rise and tall times are driven at 1ns/V.

Timing Waveforms

All Timing measurements are made at 1.5V unless otherwise noted.

FIGURE 4. TIMING WAVEFORMS

Test Load Circuits

FIGURE 5. TIVOV, TSHOV

FIGURE 6. TELOV OUTPUT HIGH ENABLE

TR, TF (8)

TIVSL (5)

TSHSL (7)

TSLIX

(6)

2.0V

0.8V

TIVOV

(1)

TEHOZ (3)

TSHOV (2)

VOH -0.1V

VOL +0.1V

TELOV (4)

3.0V

0.45V

OUTPUTS

OE

STB

INPUTS

2.27V

91

Ω

300pF

TEST

POINT

OUTPUT

(SEE NOTE)

1.5V

180

Ω

300pF

TEST

POINT

OUTPUT

(SEE NOTE)

82C83H