4-281

March 1997

82C83H

CMOS Octal Latching Inverting Bus Driver

Features

• Full 8-Bit Parallel Latching Buffer

• Bipolar 8283 Compatible

• Three-State Inverting Outputs

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max

• Gated Inputs

- Reduce Operating Power

- Eliminate the Need for Pull-Up Resistors

• Single 5V Power Supply

• Low Power Operation

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

• Operating Temperature Ranges

Description

The Intersil 82C83H is a high performance CMOS Octal

Latching Buffer manufactured using a self-aligned silicon gate

CMOS process (Scaled SAJI IV). The 82C83H provides an 8-

bit parallel latch/buffer in a 20 lead pin package. The active

high strobe (STB) input allows transparent transfer of data

and latches data on the negative transition of this signal. The

active low output enable (OE) permits simple interface to

microprocessor systems. The 82C83H provides inverted data

at the outputs.

Pinouts

82C83H (PDIP, CERDIP)

TOP VIEW

82C83H (PLCC, CLCC)

TOP VIEW

Ordering Information

PART NO.

PACKAGE

TEMP RANGE

PKG. NO

CP82C83H

20 Ld PDIP

E20.3

IP82C83H

E20.3

CS82C83H

20 Ld PLCC

N20.35

IS82C83H

N20.35

CD82C83H

20 Ld CERDIP

F20.3

ID82C83H

F20.3

MD82C83H/B

F20.3

8406702RA

SMD#

F20.3

MR82C83H/B

20 Pad CLCC

J20.A

84067022A

SMD#

J20.A

TRUTH TABLE

STB

OE

DI

DO

X

H

X

HI-Z

HL

LH

HLHL

↓

LX

†

H = Logic One

L = Logic Zero

X = Don‘t Care

HI-Z = High Impedance

↓

= Negative Transition

†

= Latched to Value of Last

Data

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

OE

GND

STB

PIN NAMES

PIN

DESCRIPTION

Data Input Pins

Data Output Pins

STB

Active High Strobe

OE

Active Low Output Enable

19

3

2

20

1

15

16

17

18

14

9

10

11

12

13

4

5

6

7

8

File Number

2971.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207