7-1064

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD4089BMS

CMOS Binary Rate Multiplier

conjunction with an up/down counter and control logic used

to perform arithmetic operations (adds, subtract, divide, raise

to a power), solve algebraic and differential equations,

generate natural logarithms and trigometric functions, A/D

and D/A conversions, and frequency division.

For words of more than 4 bits, CD4089BMS devices may be

cascaded in two different modes: an Add mode and a Multi-

ply mode (see Figures 3 and 4). In the Add mode some of

the gaps left by the more significant unit at the count of 15

are filled in by the less significant units. For example, when

two units are cascaded in the Add mode and programmed to

11 and 13, respectively, the more significant unit will have 11

output pulses for every 16 input pulses and the other unit will

have 13 output pulses for every 256 input pulses for a total of

In the Multiply mode the fraction programmed into the first

rate multiplier is multiplied by the fraction programmed into

the second multiplier. Thus the output rate will be

The CD4089BMS has an internal synchronous 4 bit counter

which, together with one of the four binary input bits, pro-

duces pulse trains as shown in Figure 6.

If more than one binary input bit is high, the resulting pulse

train is a combination of the separate pulse trains as shown

in Figure 6.

The CD4089BMS is supplied in these 16-lead outline packages:

11

+

13

=

189

16

256

256

11

x

13

=

143

16

16

256

Braze Seal DIP

H4W

Frit Seal DIP

H2R

Ceramic Flatpack

H6P

Features

• High Voltage Type (20V Rating)

• Cascadable in Multiples of 4 Bits

• Set to “15” Input and “15” Detect Output

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Standardized Symmetrical Output Characteristics

• Maximum Input Current of 1

µA at 18V Over Full Pack-

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• Numerical Control

• Instrumentation

• Digital Filtering

• Frequency Synthesis

Description

CD4089BMS is a low power 4 bit digital rate multiplier that

provides an output pulse rate that is the clock-input-pulse

when the binary input number is 13, there will be 13 output

pulses for every 16 input pulses. This device may be used in

December 1992

File Number

3329

Pinout

CD4089BMS

TOP VIEW

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

“15” OUT

C

D

SET TO “15”

OUT

OUT

VSS

INHIBIT OUT (CARRY)

VDD

A

CLEAR

CASCADE

INHIBIT IN (CARRY)

STROBE

CLOCK

B

Functional Diagram

INHIBIT

(CARRY) IN

SET TO

“15”

CLEAR

13

4

11

CLOCK

9

4 BIT

BINARY

COUNTER

7

INHIBIT (CARRY) OUT

1

“15” OUT

A

14

B

15

C

2

D

3

10

12

CASCADE

STROBE

BINARY RATE

SELECT INPUTS

RATE

SELECT

LOGIC

OUT

OUT

RATE

OUTPUTS

6

5

VDD = 16

VSS = 8