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CD4536BMS

FUNCTIONAL TEST SEQUENCE

INPUTS

OUTPUTS

COMMENTS

IN 1

SET

RESET

8-BYPASS

DECODE OUT

Q1 THRU 24

ALL 24 STEPS ARE IN RESET MODE

1011

0

1111

0

Counter is in three 8-stage section in parallel

mode

0111

0

First “1” to “0” transition of clock

1

0

-

-

-

111

255 “1” to “0” transitions are clocked in the

counter

0111

1

The 255 “1” to “0” transition

0000

1

Counter converted back to 24 stages in series

mode.

Set and Reset must be connected together

and simultaneously go from “1” to “0”

1000

1

In1 Switches to a “1”

0000

0

Counter Ripples from an all “1” state to an all

“0” state

Test Function has been included for the reduction of test

time required to exercise all 24 counter stages. This test

function divides the counter into three 8-stage sections and

255 counts are loaded in each of the 8-stage sections in par-

allel. All flip-flops are now at a “1”. The counter is now

returned to the normal 24 steps in series configuration. One

more pulse is entered into In1 which will cause the counter

to ripple from an all “1” state to an all “0” state.

Functional Test Sequence

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are derived from

the basic inch dimensions as indicated. Grid graduations are in mils

METALLIZATION:

Thickness: 11k

Å

PASSIVATION:

10.4kÅ - 15.6k

BOND PADS:

0.004 inches X 0.004 inches MIN

DIE THICKNESS:

0.0198 inches - 0.0218 inches

INTERSIL