71

Pin Descriptions

PLCC

PDIP

SYMBOL

DESCRIPTION

1

2

7

BGND

Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.

Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.

48

+5V power supply.

5

9

RINGRLY

Ring relay driver output.

610

Battery supply voltage, -24V to -56V.

711

Saturation guard programming resistor pin.

8

12

E1

TTL compatible logic input. The logic state of E1 in conjunction with the logic state of C1 determines which detector

is gated to the DET output.

9

13

E0

TTL compatible logic input. Enables the DET output when set to logic level zero and disables DET output when set

to a logic level one.

11

14

DET

Detector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered

(see Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET

output is an open collector with an internal pull-up of approximately 15k

12

15

C2

TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active,

Ringing or Standby) of the SLIC.

13

16

C1

TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active,

Ringing or Standby) of the SLIC.

14

17

nected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to AGND

to isolate the AC signal components.

15

18

AGND

Analog ground.

16

19

RSN

Receive Summing Node. The AC and DC current flowing into this pin establishes the metallic loop current that

flows between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into

the RSN pin. The constant current programming resistors and the networks for program receive gain and 2-wire

impedance all connect to this pin.

18

20

-5V power supply.

19

21

Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming

the 2-wire input impedance connects between this pin and RSN.

20

22

HPR

21

1

HPT

22

2

RD

23

3

DT

Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a compar-

ator in the SLIC with inputs DT and DR.

25

4

DR

Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a compar-

ator in the SLIC with inputs DT and DR.

26

Internally connected to output of tip power amplifier.

27

5

TIPX

Output of tip power amplifier.

28

6

RINGX

Output of ring power amplifier.

3, 10,

17, 24

N/C

No internal connection.

HC5523