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ADF4112BCPZ Datasheet(PDF) 5 Page - Analog Devices |
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ADF4112BCPZ Datasheet(HTML) 5 Page - Analog Devices |
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5 / 28 page  Data Sheet ADF4110/ADF4111/ADF4112/ADF4113 Rev. F | Page 5 of 28 TIMING CHARACTERISTICS Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 10 ns min DATA to CLOCK setup time t2 10 ns min DATA to CLOCK hold time t3 25 ns min CLOCK high duration t4 25 ns min CLOCK low duration t5 10 ns min CLOCK to LE setup time t6 20 ns min LE pulse width CLOCK DATA LE LE DB23 (MSB) DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t1 t2 t3 t4 t5 t6 Figure 2. Timing Diagram |
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