ADF4112BCPZ datasheet(26/28 Pages) AD

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ADF4110/ADF4111/ADF4112/ADF4113

Data Sheet

Rev. F | Page 26 of 28

INTERFACING

The ADF4110 family has a simple SPI® compatible serial inter-

face for writing to the device. SCLK, SDATA, and LE control the

data transfer. When latch enable (LE) goes high, the 24 bits that

have been clocked into the input register on each rising edge of

SCLK get transferred to the appropriate latch. See Figure 2 for

the timing diagram and Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

833 kHz, or one update every 1.2 µs. This is certainly more than

adequate for systems that have typical lock times in the

hundreds of microseconds.

ADuC812 Interface

Figure 38 shows the interface between the ADF4110 family and

the ADuC812 MicroConverter®. Since the ADuC812 is based

on an 8051 core, this interface can be used with any 8051 based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4110 family

needs a 24-bit word. This is accomplished by writing three 8-bit

bytes from the MicroConverter to the device. When the third

byte has been written, the LE input should be brought high to

complete the transfer.

When power is first applied to the ADF4110 family, three writes

are needed (one each to the R counter latch, N counter latch,

and initialization latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power-

down (CE input), and to detect lock (MUXOUT configured as

lock detect and polled by the port input).

When the ADuC812 is operating in the mode described above,

the maximum SCLOCK rate of the ADuC812 is 4 MHz. This

means that the maximum rate at which the output frequency

can be changed is 166 kHz.

SCLOCK

MOSI

I/O PORTS

ADuC812

SCLK

SDATA

MUXOUT

(LOCK DETECT)

ADF4110

ADF4111

ADF4112

ADF4113

Figure 38. ADuC812 to ADF4110 Family Interface

ADSP-2181 Interface

Figure 39 shows the interface between the ADF4110 family and

the ADSP-21xx digital signal processor. The ADF4110 family

needs a 24-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP-21xx family is to use the

auto buffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated.

SCLK

I/O FLAGS

ADSP-21xx

SCLK

SDATA

MUXOUT

(LOCK DETECT)

ADF4110

ADF4111

ADF4112

ADF4113

TFS

Figure 39. ADSP-21xx to ADF4110 Family Interface

Set up the word length for 8 bits and use three memory

locations for each 24-bit word. To program each 24-bit latch,

store the three 8-bit bytes, enable the auto buffered mode, and

then write to the transmit register of the DSP. This last opera-

tion initiates the autobuffer transfer.

PCB DESIGN GUIDELINES FOR CHIP SCALE

PACKAGE

The lands on the chip scale package (CP-20) are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the

pad. This ensures that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern. This ensures that

shorting is avoided.

Thermal vias may be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated in the thermal pad at 1.2 mm

pitch grid. The via diameter should be between 0.3 mm and

0.33 mm, and the via barrel should be plated with 1 oz. copper

to plug the via.

The user should connect the printed circuit board thermal pad

to AGND.

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