HMP8191 datasheet(13/32 Pages) INTERSIL

13 / 32 page

TABLE 11. CONTROL REGISTER NAMES

SUB ADDRESS

(HEX)

CONTROL REGISTER

RESET

CONDITION

08-0D

1A-1F

28-2F

30-6A

6B-6F

70-7F

product ID

output format

input format

video processing

timing I/O 1

timing I/O 2

VBI data enable

VBI data input

reserved

host control 1

host control 2

caption_21A

caption_21B

caption_284A

caption_284B

WSS_20A

WSS_20B

WSS_283A

WSS_283B

CRC_20

CRC_283

reserved

start h_blank low

start h_blank high

end h_blank

start v_blank low

start v_blank high

end v_blank

field control 1

field control 2

reserved

test and unused

phase increment

test and unused

00H

06H

80H

00H

1EH

00H

80H

00H

3FH

4AH

03H

7AH

03H

01H

13H

00H

FIGURE 10. I2C SERIAL TIMING FLOW

FIGURE 11. REGISTER WRITE PROGRAMMING FLOW

SDA

SCL

START

CONDITION

1-7

ADDRESS

R/W

ACK

1-7

DATA

ACK

STOP

CONDITION

CHIP ADDR

SUB ADDR

DATA

S = START CYCLE

P = STOP CYCLE

A = ACKNOWLEDGE

FROM MASTER

FROM ENCODER

0x40 OR

DATA WRITE

DATA

DATA READ

POINTED

TO BY

SUBADDR

POINTED

TO BY

SUBADDR

NA = NO ACKNOWLEDGE

0x41 OR

CHIP ADDR

SUB ADDR

CHIP ADDR

0x43

0x42

OPTIONAL FRAME

MAY BE REPEATED

n TIMES

OPTIONAL FRAME

MAY BE REPEATED

n TIMES

0x40 OR

0x42

HMP8190, HMP8191

HMP8191 Datasheet(PDF) 13 Page - Intersil Corporation

HMP8191 Datasheet(HTML) 13 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL