| Electronic Components Datasheet Search |
|
HMP8191 Datasheet(PDF) 21 Page - Intersil Corporation |
|
|
|||||||||||||||||||||||||||||
HMP8191 Datasheet(HTML) 21 Page - Intersil Corporation |
|
21 / 32 page ![]() 21 1 FIELD Detect Select This bit specifies whether an odd or even field is starting when the leading edge of HSYNC occurs within the FIELD Detect Window. It is ignored unless HSYNC and VSYNC are config- ured as inputs. 0 = odd field 1 = even field 0B 0 Field Detect Window Size High This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Size value. This bit is ignored unless HSYNC and VSYNC are configured as inputs. 0B TABLE 39. FIELD CONTROL REGISTER 2 SUB ADDRESS = 27H BIT NUMBER FUNCTION DESCRIPTION RESET STATE TABLE 40. PHASE INCREMENT REGISTER 0 SUB ADDRESS = 6BH BIT NUMBER FUNCTION DESCRIPTION RESET STATE 7-0 PHINC 0 (LSB) The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The PHINC value is the phase increment value of the color subcarrier generation NCO. When the BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to determine the last PHINC value loaded via the selected interface. 00H TABLE 41. PHASE INCREMENT REGISTER 1 SUB ADDRESS = 6CH BIT NUMBER FUNCTION DESCRIPTION RESET STATE 7-0 PHINC 1 The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The PHINC value is the phase increment value of the color subcarrier generation NCO. When the BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to determine the last PHINC value loaded via the selected interface. 00H TABLE 42. PHASE INCREMENT REGISTER 2 SUB ADDRESS = 6DH BIT NUMBER FUNCTION DESCRIPTION RESET STATE 7-0 PHINC 2 The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The PHINC value is the phase increment value of the color subcarrier generation NCO. When the BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to determine the last PHINC value loaded via the selected interface. 00H TABLE 43. PHASE INCREMENT REGISTER 1 SUB ADDRESS = 6EH BIT NUMBER FUNCTION DESCRIPTION RESET STATE 7-0 PHINC 3 (MSB) The 8-bit registers PHINC 0–3 are cascaded together to form a 32-bit PHINC value. The PHINC value is the phase increment value of the color subcarrier generation NCO. When the BT.656 ancillary data is selected as the PHINC source, the PHINC registers may be read to determine the last PHINC value loaded via the selected interface. 00H HMP8190, HMP8191 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |