R5F10366ASP datasheet(85/110 Pages) RENESAS

85 / 110 page

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: TA =

−40 to +105°C)

R01DS0193EJ0200 Rev.2.00

Sep 06, 2013

Page 85 of 106

(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock

output) (1/3)

(TA =

−40 to +105°C, 2.4 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main) Mode

Unit

MIN.

MAX.

SCKp cycle time

tKCY1

≥ 4/fCLK

4.0 V

≤ VDD ≤ 5.5 V,

2.7 V

≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

600

2.7 V

≤ VDD < 4.0 V,

2.3 V

≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

1000

2.4 V

≤ VDD < 3.3 V,

1.6 V

≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

2300

SCKp high-level width

tKH1

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

tKCY1/2

−150

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

tKCY1/2

−340

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

tKCY1/2

−916

SCKp low-level width

tKL1

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 30 pF, Rb = 1.4 k

tKCY1/2

−24

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 30 pF, Rb = 2.7 k

tKCY1/2

−36

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 30 pF, Rb = 5.5 k

tKCY1/2

−100

Cautions 1.

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode

for the SOp pin and SCKp pin by using port input mode register 1 (PIM1) and port output mode

CSI01 and CSI11 cannot communicate at different potential.

Remarks 1.

Rb [

Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)

load capacitance, Vb [V]: Communication line voltage

p: CSI number (p = 00, 20)

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