R5F10366ASP datasheet(92/110 Pages) RENESAS

92 / 110 page

RL78/G12

3. ELECTRICAL SPECIFICATIONS (G: TA =

−40 to +105°C)

R01DS0193EJ0200 Rev.2.00

Sep 06, 2013

Page 92 of 106

(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I

C mode)

(TA =

−40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

Conditions

HS (high-speed main)

Mode

Unit

MIN.

MAX.

SCLr clock frequency

fSCL

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

100

Note1

kHz

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

100

Note1

kHz

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

100

Note1

kHz

Hold time when SCLr = “L”

tLOW

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

4600

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

4600

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

4650

Hold time when SCLr = “H”

tHIGH

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

2700

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

2400

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

1830

Data setup time (reception)

tSU:DAT

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

1/fMCK

+ 760

Note3

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

1/fMCK

+ 760

Note3

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

1/fMCK

+ 570

Note3

Data hold time (transmission)

tHD:DAT

4.0 V

≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,

Cb = 100 pF, Rb = 2.8 k

1420

2.7 V

≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,

Cb = 100 pF, Rb = 2.7 k

1420

2.4 V

≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,

Cb = 100 pF, Rb = 5.5 k

1215

Notes 1.

The value must also be equal to or less than fMCK/4.

Set tSU:DAT so that it will not exceed the hold time when SCLr = "L" or SCLr = "H".

Cautions 1. Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin

and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode

characteristics with TTL input buffer selected.

2. IIC01 and IIC11 cannot communicate at different potential.

(Remarks are listed on the next page.)

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