Self tests for SPC564Ax core subsystem

AN3018

10/24

Doc ID 16081 Rev 2

3

Self tests for SPC564Ax core subsystem

3.1

Flash self tests

Several Flash tests can be implemented:

–

Flash integrity test

–

Flash ECC logic verification

–

Flash address decoder

–

Flash margin mode

Some SPC564Ax derivatives, like the 4 MB version, have two Flash modules. The tests

described below can be implemented on any of the flash modules in SPC564Ax devices.

Not having valid content in some of the memory locations of the sectors to be checked may

lead to limitation to flash sectors that do not have EEPROM data. This may happen for

sectors or data sets in EEPROM emulation area, as the programming or erasing may be

interrupted.

3.1.1

Flash integrity check

Principle: the Flash integrity test uses a proprietary address sequence to compute a 32-bit

signature over the flash content over selected flash sectors. The check includes user data

bits but also the ECC bits.

Result: once the operation is completed, the results of the reads can be checked by reading

the MISR value (stored in UMISR0-4), to determine if an incorrect read or ECC detection

was noted. The internal MISR calculator is a 32 bit register. The MISR can be seeded to any

value by initializing the UMISR0-4 registers before starting the test.

Resource availability: the Flash module is not available during this test.

The 128-bit data, 16-bit ECC data and the single and double ECC errors of the two double

words are therefore captured by the MISR through five different read accesses at the same

location. The whole check is done through five complete scans of the memory address

space:

1.

The first pass scans only bits 31-0 of each page.

2.

The second pass scans only bits 63-32 of each page.

3.

The third pass scans only bits 95-64 of each page.

4.

The fourth pass scans only bits 127-96 of each page.

5.

The fifth pass scans only the ECC bits (8 + 8) and the single and double ECC errors (2

+ 2) of both double words of each page.

The 128-bit data and the 16 ECC data are sampled before the eventual ECC correction,

while the single and double error flags are sampled after the ECC evaluation.

Only data from existing and unlocked locations is captured by the MISR.

There is no restriction on the number of times the test can be performed.

For more details on this test, please refer to device reference manual (see Section A.1:

Reference documents).