Anatomy of a parasitic bipolar transistor

AN1009

1

Anatomy of a parasitic bipolar transistor

Figure 1: "Cross-section of an NPN parasitic bipolar transistor" shows the cross-section of

a CMOS gate, with one MOSFET formed directly in the N-type substrate, and the other in a

P-well. Under certain conditions, the P-well can start to behave as the base region of a

parasitic bipolar NPN transistor, with the N-type substrate as its collector region, and the

N+ diffusion contact of the MOSFET as its emitter region.

Figure 1: Cross-section of an NPN parasitic bipolar transistor

The P-well is held at ground, so the parasitic NPN transistor should never turn on. If,

though, a negative pulse is applied to the pad, and hence to the emitter of the parasitic

NPN transistor, the transistor would be put into its conducting mode. Once the pad is taken

When the memory device is being powered by the external power source, the effect of this

extra parasitic current will be negligible, and will be compensated for by the external power

source. When the memory device is being powered from the internal battery, though, the

battery is unable to compensate for the extra current, and so the supply voltage will fall. As

soon as the supply voltage falls below a critical value, SRAM cells in the memory array will

cease to hold their stored data reliably.

The parasitic bipolar transistor starts to turn on when the pad is taken to about -0.6 V. In

battery mode, the impact on the substrate will start to be felt once the current drain through

the bipolar transistor is approximately -0.6 mA. The substrate will be pulled to

approximately 1.0 V once the current through the bipolar transistor reaches -1.5 mA. As the

ground, thus leaving the SRAM array completely unpowered.

2/7

DocID006391 Rev 2

PAD

(NEGATIVE PULSE)

P+

N+

P+

N+

GATE

VCC

GROUNDED

P-WELL

N-SUBSTRATE

GATE

P+

N+

VSS

N+

SUBSTRATE

VCC

GROUNDED P-WELL

INTERNAL POWER