May 2012

Doc ID 10604 Rev 2

1/9

AN1572

Application note

Power-down time-stamp function in serial real-time clocks (RTCs)

By Doug Sams

Introduction

Power-down time stamp and the Halt bit

Many serial RTC devices from STMicroelectronics include a feature known as power-down

time stamp. One register bit, Halt (HT), controls this feature. It is important that users

understand three things about the HT bit in order to ensure correct operation of these

devices.

1.

Upon power-up, prior to writing any of the clock/calendar registers - that is, prior to

writing any address in the range 00h to 07h - the user must first clear the HT bit by

writing it to 0 (in bit 6 of address 0Ch).

2.

Writing to addresses 00h to 07h (upon power-up) without first clearing the HT bit will

result in the counters being overwritten, thus corrupting the time/date.

3.

Before the HT bit is cleared, reads of the device will return the time of power-down (or,

in the case of the M41T82/83/93, the time of the last read or write prior to power-down).

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