Calibrating the M41T83 using analog calibration

AN2678

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As the watch crystal curve of Figure 1 predicts, the RTC oscillator will tend to be slow more

often than fast, so the adjustment range of the part is asymmetric; there is more range for

increasing the RTC oscillator speed than for slowing it down.

For the M41T82, M41T83 and M41T93 RTCs, the smallest incremental adjustments are

step sizes of approximately 0.25 pF. One step of 0.25 pF is roughly 0.5 ppm.

Since this algorithm uses a binary tree approach, each increment of capacitance must be a

power of 2 times 0.25 pF. That is, capacitance will be added and/or subtracted in

increments of 8 pF, 4 pF, 2 pF, 1 pF, 0.5 pf or 0.25 pF.

Thus, although up to 18.0 pF can be subtracted or up to 9.75 pF can be added, the power of

2 restriction constrains these limits to –16 pF and +8 pF, respectively. As a result, this

algorithm does not use the total available adjustment range, but that will not be a problem in

most applications.

For example, with this approach, when capacitance is to be added, instead of starting at half

the maximum available, ½ x 9.75 pF (= 4.875 pF), the power of 2 nearest that is used, which

is 4 pF. Similarly, for removing capacitance, the most that can be subtracted is 18 pF, so the

algorithm starts at the power of 2 nearest ½ x 18, or 8 pF.

Returning to Figure 5, after making the first measurement of FT, if capacitance is added, as

shown on the right, the ACAL value is adjusted to 4 pF. Then, progressively smaller

increments of capacitance are added or removed, until the frequency error measured on the

FT pin is minimized.

If, in Figure 5, the first test of the FT signal indicates that capacitance must be removed (that

the RTC is slow), the analog calibration register is set to –8 pF and then progressively

smaller increments of capacitance are added or removed.

Each time the analog calibration register is adjusted, the oscillator must be allowed time to

settle before taking another measurement. This is shown at the top of Figure 5, but not

shown in successive steps for the sake of brevity. However, it is still required each time the

register is written.

Using this binary approach, each of the 25 pF capacitors can be increased by up to 7.75 pF

or decreased by up to 15.75 pF. While these adjustment limits are slightly less than the

absolute limits available - up to a 9.75 pF increase or 18 pF decrease - they should cover all

except the most extreme cases of RTC oscillator error.

It may be possible to use the wider, available adjustment limits in an adaptive calibration

scheme like this one, but when increments other than powers of 2 are used, the algorithm

becomes much, much more complex and thus may not be as easy for users to implement.

Once the final calibration bit has been determined, the user should record the value in non-

volatile memory so that it can be retrieved by the microprocessor when necessary.

If a frequency counter was used to perform the measurements during the analog calibration

procedure, the user should immediately follow that with the additional step of using the

microprocessor and its timer to measure the period of the FT signal out of the real-time

clock as described in Section 1.3 and 1.4. This is done to establish the initial error, if any, in

the microprocessor’s timing chain at room temperature. This value should also be stored in

non-volatile memory.