CSE IP block overview

AN4240

6/30

Doc ID024209 Rev 2

After system boot, the core comes out of reset and executes reset code from the module

ROM. This code will load the firmware from the secure flash into the module RAM and start

executing from there. This reduces the flash accesses by the crypto core.

The AES block is a slave to the crypto internal bus. It processes the encryption (plain text to

ciphertext) and decryption (ciphertext to plaintext) and offers AES CMAC authentication.

The 32-bit secure core works at 120 MHz with a throughput of 100 Mbit/sec.