AN1451 datasheet(4/43 Pages) STMICROELECTRONICS

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AN1451 APPLICATION NOTE

4/43

above VS, due to the PCB inductance and voltage drop across the high-side (integrated) freewheeling diode,

as the current reverses direction and flows into the bulk capacitor. It turns out that, in fast decay, the highest

differential voltage is observed between the two

OUT pins of the same bridge, at the beginning of the off-time,

and this must always be kept below 60V [3]. The same high voltage condition exists when a step is made and

the direction of current flow reverses in the bridge.

Figure 3. Currents and voltages during the

dead time at the beginning of the off-time.

Figure 4 shows the voltage waveforms at the two OUT pins referring to a possible practical situation, with a peak

output current of 2.8A, VS = 52V, RSENSE = 0.33Ω, TJ = 25°C (approximately) and a good PCB layout. Below

ground spike amplitude is -2.65V for one output; the other

OUT pin is at about 57V. In these conditions, total

differential voltage reaches almost 60V, which is the absolute maximum rating for the DMOS. Keeping differen-

tial voltage between two Output pins belonging to the same Full Bridge within rated values is a must that can

be accomplished with proper selection of Bulk capacitor value and equivalent series resistance (ESR), accord-

ing to current peaks and chopping style and adopting good layout practices to minimize PCB parasitic induc-

tances (see below) [3].

SENSE

OUT

SENSE*I

SENSE*I+VF(Diode)

PCB Parasitic

Inductance

PCB Parasitic

Inductance

Bulk Capacitor

Equivalent Circuit

ESR

ESL

SENSE

S+VF(Diode)

Dangerous

High Differential Voltage

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