Main characteristics and circuit description

AN3118

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Doc ID 16847 Rev 2

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Main characteristics and circuit description

The main characteristics of the SMPS are listed below:

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Line voltage range: 90 to 265 Vac

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Regulated output voltage: 400 V

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Rated output power: 250 W

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Minimum switching frequency: 46 kHz

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Minimum estimated efficiency: 93 % (@ Vin=90 Vac, Pout=250 W)

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Maximum ambient temperature: 50 °C

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PCB type and size: single side, 35 µm, CEM-1, 88 x 116 mm

This demonstration board implements a power factor correction (PFC) pre-regulator, 250 W

continuous power, delivering a regulated 400 V rail from a wide range mains voltage and

providing for the reduction of the mains harmonics, therefore meeting the European

EN61000-3-2 or the Japanese JEITA-MITI standard. The regulated output voltage is

typically the input for the cascaded isolated DC-DC converter that will provide the output

rails required by the load.

The power stage of the PFC is a conventional boost converter, connected to the output of

the D1 rectifier bridge. It is completed by the L2 coil, the D3 diode, and the C5 capacitor.

The boost switch is represented by the power Q1 and Q2 MOSFETs, connected in parallel.

The NTC R1 limits the inrush current at switch on. It is connected on the DC rail, in series to

the output electrolytic capacitor, in order to improve the efficiency during low line operation.

In fact the RMS current flowing into the output stage is lower than current flowing into the

input stage at the same input voltage. The board is equipped with an input EMI filter

necessary to filter the switching noise coming from the boost stage.

At startup the L6563H (U1) is powered by the Vcc electrolytic capacitor C9 which is charged

via High Voltage Start up (HVS) pin #9. The HVS pin, able to withstand 700V, is connected

directly to the rectified mains voltage. A 0.85 mA (typ.) internal current source charges the

C9 capacitor connected between Vcc pin #16 and GND pin #14 until the voltage on the Vcc

pin reaches the startup threshold. The L2 secondary winding and the charge pump circuit

(C6, R2, D4 and D5) generate the Vcc voltage, powering the L6563H during normal

operations. The L2 secondary winding is also connected to the L6563H pin #13 (ZCD)

demagnetized, needed by the internal logic to trigger a new switching cycle.

The divider R4, R8, R12 and R15 provides to the L6563H multiplier the information of the

instantaneous mains voltage that is used to modulate the peak current of the boost.

The R3, R6, R7 with R9 and R10 resistors are dedicated to sensing the output voltage and

feed to the L6563H the feedback information necessary to regulate the output voltage. The

C7, R13, and C10 components are the error amplifier compensation network necessary to

get the required loop stability.

The peak current is sensed by R23 and R24 resistors in series to the MOSFET and the

signal is fed into pin #4 (CS) of the L6563H via the filter by R20 and C14.