Block diagram and pin function description

AN3352

8/26

Doc ID 018526 Rev 3

interface TEN bit. The rise and fall edges are controlled to be in the 5 µs to 15 µs range, 8 µs

amplitude as well as the DSQIN pin.

1.8

DiSEqC communication

The following steps must be taken to ensure the correct implementation of the DiSEqC

communication:

●

T0: before starting the DiSEqC transmission. The TTX function must be activated

(through the TTX pin or TTX I²C bit)

●

T1: after 500 µs minimum, the IC is ready to receive the DiSEqC code through the

DSQIN pin (or, alternatively, the TEN I²C bit can be set to HIGH to activate the 22 kHz

burst)

●

T2: when the transmission has elapsed, the TTX function is set to LOW (through the

TTX pin or TTX I²C bit) not earlier than 200 µsec after the last falling edge of the

DiSEqC code.

1.9

Linear post-regulator, modulator and protection

The output voltage selection and the current selection commands join this block, which

manages the LNB output function. This block gives feedback to the I²C interface from the

diagnostic block, regarding the status of the thermal protection, overcurrent protection, and

output settings.

1.10

Pin description

The LNBH24L is available in an exposed pad QFN-32 package for surface mount assembly.

Figure 5 shows the device pinout and Table 3 briefly summarizes the pin function.

Figure 4.

DiSEqC timing control

LNBout

DSQIN

TTX

DiSEqC Transmit Mode

DiSEqC Receive Mode

> 500µs

> 200 µs

µ

LNBout

DSQIN

TTX

DiSEqC Transmit Mode

DiSEqC Receive Mode

> 500µs

> 200 µs

µ