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AN4069 Datasheet(PDF) 8 Page - STMicroelectronics |
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AN4069 Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 16 page ![]() Output dV/dt circuit AN4069 8/16 Doc ID 022926 Rev 1 5 Output dV/dt circuit The demo board comes with no CdV/dt mounted. In this condition, after an initial delay time of typically 500 µs for the STEF05 and 350 µs for the STEF12, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. The total time from the enable signal going high and the output voltage reaching the nominal value is typically 1 ms. The output voltage slew rate can be customized by mounting the dV/dt capacitors (C1, C2). The suggested values range is 10 pF to 1 nF. Given the desired time interval Δt during which the output voltage goes from zero to its maximum value, the capacitance to be added on the Cdv/dt pin can be calculated using the following theoretical formulas: ● STEF05 dV/dt setting Cdvdt = 50 × 10-9Δt - 30 × 10-12 ● STEF12 dV/dt setting Cdvdt = 24 × 10-9Δt - 30 × 10-12 Figure 6. STEF05 delay time and VOUT ramp-up time |
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