AN4205 datasheet(6/23 Pages) STMICROELECTRONICS

6 / 23 page

Input stage of the AC/DC converter

AN4205

6/23

Doc ID 023929 Rev 1

ratio and adds to the input voltage VIN, giving a much higher voltage on the drain of the

Power MOSFET.

Equation 1

Before starting the design of the converter, some parameters need to be set.

Figure 3.

Details of the Power MOSFET drain voltage

The drain voltage of the Power MOSFET device is:

Equation 2

The Vfl reflected voltage depends on a proper NP/NS transformer ratio. In particular the

maximum voltage rating of the Power MOSFET and the VR reverse voltage across the

output diode relates to this transformer ratio. A lower NP/NS requires a higher VR on the

diode, while VDS of the Power MOSFET is decreased. However, a higher transformer ratio

implies a higher voltage stress on the Power MOSFET, while VR is decreased.

The Vspike leakage inductance overvoltage is due to energy stored in the mutual inductance

of the transformer primary side which is not completely transferred to the secondary. When

the leakage inductance is demagnetized, the energy can be transferred to the secondary. In

order to minimize this delay, the voltage across the primary inductance should be as high as

possible.

The Vmargin should be 20% of the VDSS of the Power MOSFET device.

In accordance with these explanations we have chosen:

Vspike=160 V

Vmargin=160 V

Hence, a device with VDSS = 800 V (STD3NK80Z) has been chosen. This selection will

allow using a clamp circuit with a lower operation time and having a safety margin around

the voltage rating on the drain pin.

out

diode

()

-------

VDS

Vin

VDSmin

VDSs

Llk & Cd

Lp & Cd

AM16369v1

DSS

spike

min

arg

AN4205 Datasheet(PDF) 6 Page - STMicroelectronics

AN4205 Datasheet(HTML) 6 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL