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AN4662 Datasheet(PDF) 9 Page - STMicroelectronics

Part # AN4662
Description  This document describes the low-voltage 3-axis digital output linear MEMS accelerometer provided
PDF  43 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN4662 Datasheet(HTML) 9 Page - STMicroelectronics

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AN4662
Operating modes
2.1
Power-down mode
When the device is in power-down mode, almost all internal blocks of the device are
switched off to minimize power consumption. Digital interfaces (I
2C and SPI) are still active
to allow communication with the device. The content of the configuration registers is
preserved and the output data registers are not updated, therefore keeping the last data
sampled in memory before going into power-down mode.
During power-down mode the Interrupt pins continue to be driven at the last logical state.
2.2
Active mode
In active mode, data are generated at the output data rate (ODR) selected through the
ODR[2:0] bits of CTRL1 register. Six different ODRs can be selected in order to guarantee
desired application bandwidth: 800 Hz, 400 Hz, 200 Hz, 100 Hz, 50 Hz and 10 Hz.
The three acceleration axes can be individually enabled through the Zen, Yen, and Xen bits
of CTRL1 register. All combinations of single, two or three axes can be applied; output
registers related to disabled axes are forced to value 0000h.
Data interrupt generation and the FIFO buffer are active and configurable respectively
through the IG_CFGx (30h, 36h) and FIFO_CTRL (2Eh) registers.
The Activity/Inactivity recognition function can be enabled to reduce system power
consumption.
2.3
Data stabilization time
The LIS2HH12 reading chain contains low-pass filtering to improve signal-to-noise
performance and to reduce aliasing effects. For this reason the settling time of the filters
must be considered when the device is switched from power-down to active mode or when
the ODR is changed.
Table 4: "Number of samples to be discarded" clarifies the number of samples to be
discarded depending on the internal filter bandwidth and output data rate selection.
Bandwidth can be changed by setting the BW [2:1] bits in CTRL4 register and the output
data rate can be changed by setting the ODR [2:0] bits in CTRL1.
Table 4: Number of samples to be discarded
ODR [Hz]
BW = 400 Hz
BW = 200 Hz
BW = 100 Hz
BW = 50 Hz
10
1
-
-
-
50
1
-
-
-
100
1
1
1
1
200
1
1
1
4
400
1
1
4
7
800
1
4
7
14
DocID027579 Rev 1
9/43



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