Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

UPD4990AC Datasheet(PDF) 2 Page - NEC

Part # UPD4990AC
Description  SERIAL I/O CALENDAR & CLOCK CMOS LSI
PDF  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD4990AC Datasheet(HTML) 2 Page - NEC

  UPD4990AC Datasheet HTML 1Page - NEC UPD4990AC Datasheet HTML 2Page - NEC UPD4990AC Datasheet HTML 3Page - NEC UPD4990AC Datasheet HTML 4Page - NEC UPD4990AC Datasheet HTML 5Page - NEC UPD4990AC Datasheet HTML 6Page - NEC UPD4990AC Datasheet HTML 7Page - NEC UPD4990AC Datasheet HTML 8Page - NEC UPD4990AC Datasheet HTML 9Page - NEC Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 20 page
background image
µPD4990A
2
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VDD
− VSS
−0.5 to 7.0
V
Input Voltage
VIN
VSS
−0.3 to VDD +0.3
V
Operating Temperature Range
Topt
−40 to +85
°C
Storage Temperature Range
Tstg
−65 to +125
°C
Output Terminal Voltage
VOUT
−0.5 to 7.0
V
ELECTRICAL CHARACTERISTICS (f = 32.768 kHz, CG = CD = 20 pF, CI = 20 k
Ω, Ta = 25 °C)
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
Operating Voltage
VDD
− VSS
2.00
5.50
V
820
µAVDD − VSS = 3.60 V
Current Consumption
IDD
100
µAVDD − VSS = 5.50 V
VDD
− VSS = 2.0 to 5.5 V
Low Level Output Voltage
VOL
0.4*
V
IOL = 500
µA
CLK Input Frequency
fCLK
DC
500
kHz
VDD
− VSS = 2.0 V, Duty 50 %
Input Leakage Current
IIN
±1
µAVDD − VSS = 5.50 V
High Level Input Voltage
VIH
0.7 VDD
VDD
V
Low Level Input Voltage
VIL
VSS
0.3 VDD
V
* TP and DATA OUT are N-channel open drain output.
A.C. ELECTRICAL CHARACTERISTICS (f = 32.768 kHz, VDD
− VSS = 2.0 V, Ta = 25 °C)
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
C0 to 2, CS
− STB Set-up Time
tSU
1
µs
STB Pulse Width
tSTB
1
µs
C0 to 2, CS
− STB Hold Time
tHLD
1
µs
STB LATCH Delay Time
td1
1**
µs
except Time Read mode
CLK-DATA OUT Delay time
td(c-o)
1
µsRL = 33 kΩ, CL = 15 pF
DATA IN Set-up Time
tDSU
1
µs
DATA IN Hold Time
tDHLD
1
µs
** Note: When a function mode is Time Read mode (other than Test mode), STB LATCH delay time is 20
µs MAX.
(td2).



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com