10/17

MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324

4.5 CAN CLOCK

CAN clock is also divided leading to a slower baudrate. Therefore in slow mode the bit timing

must be adjusted or the CAN cell must be put in sleep mode.

5 REGISTER MAP

In the ST72521/321R, 321/324J, some register addresses and bit locations are changed.

These changes have made it possible to use the free locations to add new features.

Note: For easy software migration, two general rules have to be followed:

n

All “reserved” byte memory areas must never be “read” or “write”.

n

All “reserved” or “unused” bits must be left unchanged when accessing the byte.

5.1 REGISTER ADDRESS

These changes are classified in four groups:

1. I/O port register addresses changed

2. Miscellaneous registers changed (see Section 5.2 for more details)

3. MCCSR register address moved

4. ADC registers swapped

Note: These register address changes can be easily performed if you group all the register

definitions in a single header file.