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EEPROM Emulation with STR71x

1.3 DIFFERENCE IN ERASE TIME

The difference in erase time is the other important difference between stand-alone EEPROMs

and emulated EEPROM with embedded-Flash. Unlike Flash, EEPROM does not require a

block erase operation to free-up space before write. This means that some form of software

management is required to store data in Flash. Moreover, as the erase process of a block in

the Flash takes few seconds, power shut-down and other spurious events that may interrupt

the erase process (ex: reset) should be considered when designing the Flash management

software. This means that to design a robust Flash management software it is necessary to

have a deep understanding of the Flash erase process.

The Flash erase process is split in 3 phases:

– phase1: write all bits to 0, starting from the initial content. An interrupt during this phase will

result in some memory cells being at “0” logic level and the rest of the memory cells will still

contain their initial content.

– phase2: write all bits to 1, starting from the all “0” configuration. The longer the time before

this phase is interrupted, the higher the number of cells will return a “1” logic level. The rest

of the memory cells will contain their initial content, their content can be considered as totally

random.

– phase3: equalization. This phase is necessary to recover over-erased cells. The Flash man-

agement software for EEPROM emulation should guarantee that this phase was successful-

ly completed before programming in this bank.

The consequence of an interrupt during phase2 is that a single bit approach should be avoided

to flag the completion of the erasing process (find more details in section 2.5 on page 6).

The consequence of an interrupt during phase1 and/or phase2 is that it is recommended to

have fixed data inside the emulated EEPROM so that a checksum can be run to tell which

Flash bank keeps the valid data.

The most important point is to ensure that the Flash has been completely erased (phase3 was

not interrupted) before programming data inside a bank.

Note The design of Flash software management is easier if programming in a new bank is always made

just after erasing of this bank (when erasing of one bank is necessary).

1.4 ADDITIONAL INFORMATION ON FLASH

Incremental programming: the Flash controller will accept to program a word that is already

programmed if the new word is adding more “0” bits.

Programming completion: programming completion is important to guarantee data retention

time; the programming is complete when the Flash controller status indicates the end of pro-

gramming without showing any error flag. If programming is interrupted (ex: supply fail, CPU

reset), the cells of the word being programmed will be partially programmed. This can result in

unstable “0”s when reading this word.