3 STR73x low power modes

AN2202

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7.

On wake-up from STOP mode, the CMU automatically selects the 2MHz RC-Oscillator

clock as input clock to the PRCCU.

To further reduce power consumption during STOP mode, it is possible to:

●

Disable the main voltage regulator by writing ‘1’ in bit VRLPW in the PRCCU_VRCTR

register.

●

Minimize the low power voltage regulator current capability by setting the bit 0 and 1 of the

system configuration register 1 (LPVRCC(1:0)).

Note:

After exit from STOP mode, the Flash and the main voltage regulator are re-enabled

automatically if they were switched off during the STOP mode

3.2.5

HALT mode

The HALT sequence is initiated with the following procedure:

●

set the EN_HALT bit in the PRCCU_SMR and clear the SRESEN bit in the PRCCU_CCR

●

then set the HALT bit in the PRCCU_CCR.

Caution:

Wake-up from HALT mode is only possible by means of an external or LVD reset.

Note:

Minimize the low power voltage regulator current capability by setting the bit 0 and 1 of the

system configuration register 1 (LPVRCC(1:0)).