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AN2556 Datasheet(PDF) 25 Page - STMicroelectronics |
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AN2556 Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 35 page ![]() AN2556 Modified registers 25/35 Access to the X-Peripherals are configured through three pairs of specific X-Bus configuration registers, equivalent to the External Bus register BUSCONx and ADDRSELx. Therefore several X-Peripherals sharing the same pair leading to the point that accesses a disabled X-Peripheral are only redirected to external memory if all the other X-Peripherals sharing the same pair of registers are disabled. This gives the following groups: ● CAN1, CAN2, XASC, XSSC, XI2C, XPWM, XRTC and XMISC: accessing to range 00’E800h-00’EFFFh are redirected to external memory only if all corresponding bits are cleared. ● XRAM1: accessing to range 00’E000h-00’E7FFh are redirected to external memory if bit XRAM1EN is cleared. ● XRAM2, XFLASH: accessing to range 09’0000h-0F’FFFFh (default value in XADRS3 register, refer to Section 4.1: XADRS3 register on page 26) are redirected to external memory if bits XRAM2EN and XFLASHEN are cleared. 3.1.1 Hardware impacts None. 3.1.2 Software impacts None, if ST10F269Zx software is not written to the reserved bit. 5 XFLASHEN XFlash Enable Bit 0: Access to the Flash Registers are disabled. The on-chip Flash cannot be programmed. 1: Access to the Flash Registers are enabled. The on-chip Flash can be programmed. 6 XPWMEN XPWM Enable 0: Access to the XPWM module is disabled, external access performed. 1: The XPWM module is enabled and can be accessed. 7 XASCEN XASC Enable Bit 0: Access to the XASC is disabled, external access performed. 1: The XASC is enabled and can be accessed. 8 XSSCEN XSSC Enable Bit 0: Access to the XSSC is disabled, external access performed. 1: The XSSC is enabled and can be accessed. 9X12CEN X12C Enable Bit 0: Access to the X12C is disabled, external access performed. 1: The X12C is enabled and can be accessed. 10 XMISCEN XBUS Additional Features Enable Bit 0: Access to the Additional Miscellaneous Features is disabled. 1: The Additional Features are enabled and can be accessed. 11:15 - Reserved Table 15. XPERCON register description (continued) Bit Bit name Function |
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