AN2641 datasheet(8/37 Pages) STMICROELECTRONICS

8 / 37 page

CLCD panel programmable parameters

AN2641

8/37

Doc ID 14027 Rev 1

Figure 2 summarizes all the synchronization timings. The horizontal retrace time is the sum

of the horizontal back porch, the horizontal front porch and the horizontal sync width, while

the vertical retrace time is the sum of the vertical back porch, the vertical front porch and the

vertical sync width.

The horizontal front porch is the time from picture to sync and horizontal back porch is the

time from sync to picture.

The vertical front porch is the time from picture to sync and the vertical back porch is the

time from sync to picture.

Figure 2.

CLCD panel layout

2.1.3

Dimension related registers

HBP, 8-bit [31:24] field in the LCD-Timing1 register: specifies the number of pixel

clock periods inserted at the beginning of each line or row of pixels. After the line clock

for the previous line has been de-asserted, the value in HBP counts the number of pixel

clocks to wait before starting the next display line. HBP can generate a delay of 1-256

pixel clock cycles.

HFP, 8-bit [23:16] field in the LCD-Timing1 register: sets the number of pixel clock

intervals at the end of each line or row of pixels, before the LCD line clock is pulsed.

vertical back porch

vertical front porch

vertical sync pulse width

Y-res

horiz

back

porch

horiz

sync

pulse width

horiz

front

porch

X-res

AN2641 Datasheet(PDF) 8 Page - STMicroelectronics