November 2007

Rev 1

1/18

AN2657

Application note

An innovative verilog model for predicting

LDMOS DC, small and large signal behavior

Introduction

To reduce the design cycle time and cost for wireless applications it is useful to have models

that can help RF Engineers predict and simulate the behavior of RF power transistors.

Recently, STMicroelectronics has been strongly focused on developing new models for RF

LDMOS power transistors.

The model introduced here is simple in concept, and describes with good approximation

DC, small signal S-parameter and large signal behavior, and could be a starting point for

designers in developing their new applications. This model has been implemented in Agilent

Advanced Design System, in verilog Language, and includes the parasitic elements of the

package, as well as a thermal node which takes self heating effects into account.

In this applicatio note we will briefly describe how to extract the model parameters for the

PD54003L-E device, which is a 3 W - 7.2 V - 500 MHz LDMOS housed in a PowerFLAT

plastic package (5 x 5 mm). As an internally unmatched device, the PD54003L-E can be

used in various portable applications over HF, VHF and UHF frequency bands. At the end of

this note we will validate this new model using ST's DB-54003L-175 demoboard, especially

designed for 2-way portable radio applications using PD54003L-E over the 135-175 MHz

frequency band.

Thanks to their cost effectiveness and high performance, LDMOS devices are widely used

in radio frequency applications, ranging from digital communication infrastructures (cellular

base stations) to low cost portable radios (private mobile radios) commonly known as

walkie-talkies.

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