Summary of features

AN2658

10/23

Doc ID 14152 Rev 2

2.7

Data storage

The 10 bits of ADC converted data are stored in two 8-bit registers (and in ADC1 type also

in the buffer registers - see Figure 6.: Data alignment).

The STM8 ADC has selectable data alignment. You can choose to left or right align the 10-

bit ADC result in the two 8-bit data registers.

You must read the data registers in a particular order to ensure that the data retrieved from

the registers is consistent (resulting from the same conversion). When the first data register

is read, the second data register is latched so it can be read later and to prevent it being

overwritten by the next conversion. The order in which you must read the data registers

depends on the alignment mode. In right alignment mode, the LSB must be read first and

then the MSB. In left alignment mode, the MSB must be read first and then the LSB.

Figure 6.

Data alignment

2.8

Extended functions

These extended functions are present only in devices with ADC1.

2.8.1

Buffers

Devices with ADC1 have a set of registers for data storage which are used when buffered

mode is enabled. The converted data are stored cyclically in these registers (ring buffer).

This makes data storage and collection more efficient (less CPU load and less data buffer

overrun issues).

The number of data buffer registers is equal to the number of ADC1 input channels and

depends on the STM8 device type.

2.8.2

Buffer overrun flag

This flag is set when the values in the ADC1 data buffer registers are overwritten before

being read by the CPU. The user firmware can use this flag detect an overrun event and can

then perform appropriate actions (for example restart A/D conversion).

D1 D0

D1 D0

D3 D2

D5 D4

D7 D6

D9 D8

D9 D8

D3 D2

D5 D4

D7 D6

ADC_DRH

70

ADC_DRL

70

ADC_DRH

70

ADC_DRL

70

Left alignment mode:

Right alignment mode: