July 2010

Doc ID 17761 Rev 1

1/16

AN3250

Application note

M24LR64-R

Multi-bank reference design description and settings

1

Introduction

The M24LR64-R multi-bank reference design has been created to help users increase the

memory density of their Dual Interface EEPROM, and has been designed in a way that will

minimize the antenna size and the I²C interface footprint on the PCB.

STMicroelectronics has prepared two reference designs:

●

ANT4-M24LR-A is a 2-bank reference design with a 128-Kbit EEPROM user memory

●

ANT5-M24LR-A is a 4-bank reference design with a 256-Kbit EEPROM user memory

The basic principle is to connect several M24LR64-R devices in parallel on the same I²C bus

(in compliance with I²C specifications) and for them to share one single antenna.

This application note describes how the M24LR64-R Multi-Bank reference design works

from the schematics and design perspective, and explains how to configure and use it.

Figure 3.

Design overview

Figure 1.

ANT4-M24LR-A design

Figure 2.

ANT5-M24LR-A design

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