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PD16724 Datasheet(PDF) 21 Page - Renesas Technology Corp

Part # PD16724
Description  480-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALE)
PDF  26 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

PD16724 Datasheet(HTML) 21 Page - Renesas Technology Corp

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Data Sheet S16086EJ1V0DS
19
µµµµPD16724
Electrical Characteristics (TA =
−−−−10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 12.0 to 15.0 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Input leakage current
IIL
±1.0
µA
High-level output voltage
VOH
STHR (STHL), IOH = 0 mA
VDD1
− 0.1
V
Low-level output voltage
VOL
STHR (STHL), IOL = 0 mA
0.1
V
Pull-up/pull-down resistance
RPU
VDD1 = 3.3 V,
80
200
500
k
Ω
MODE1, MODE2, SRC1, SRC2, LPC
γ -corrected resistance
Rγ
TA = 25
°C, VDD2 = 15.0 V,
7.9
15.8
31.6
k
Ω
V0 to V8 = V9 to V17 = 7.0 V
Driver output current
IVOH
VX = 11.0 V, VOUT = 10.0 V
Note1
−40
mA
IVOL
VX = 1.0 V, VOUT = 2.0 V
Note1
40
mA
Output voltage deviation
∆VO
TA = 25
°C, VSS2 + 1.0 V to VDD2 − 1.0 V
±10
±20
mV
∆VP-P1
VX = 7.0 to 8.0 V
Note1
±5
±10
mV
∆VP-P2
VX = 4.0 to 11.0 V
Note1
±7
±15
mV
Output swing voltage difference
deviation
∆VP-P3
VDD1 = 3.3 V,
VDD2 = 15.0 V,
TA = 25
°C
VX = 1.0 to 14.0 V
Note1
±10
±20
mV
Logic part dynamic current
consumption
IDD1
VDD1
Note2
1.0
15.0
mA
Driver part dynamic current
consumption
IDD2
VDD2, with no load
Note2
12.5
40.0
mA
Notes 1. VX refers to the output voltage of analog output pins S1 to S480.
VOUT refers to the voltage applied to analog output pins S1 to S480
2. fSTB = 77 kHz, fCLK = 40 MHz
The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured
values in the dot checkerboard input pattern.
Switching Characteristics (TA =
−10 to +75°°°°C, VDD1 = 2.3 to 3.6 V, VDD2 = 12.0 to 15.0 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Start pulse delay time
tPLH1
CL = 15 pF, 2.3 V
≤ VDD1 < 3.0 V
15
ns
CL = 15 pF, 3.0 V
≤ VDD1 ≤ 3.6 V
12
ns
Driver output delay time
tPLH2
Note
VDD2 = 15.0 V, TA = 25
°C,
5
µs
tPLH3
Note
CL = 100 pF, RL = 10 k
Ω
10
µs
tPHL2
Note
5
µs
tPHL3
Note
10
µs
Input capacitance
CI1
logic input, except STHR (STHL),
TA = 25
°C
510
pF
CI2
STHR (STHL), TA = 25
°C10
15
pF
Note tPLH2, tPHL2 refer to the arrival time from falling edge of STB to target voltage
±10% (condition: VO = 0.2 V ↔14.8
V)
tPLH3, tPHL3 refer to the arrival time from falling edge of STB to target voltage
±0.02 V (condition: VO = 3.0 V ↔13.0 V)
<Test Condition>
CL1
RL1
RLn = 2 k
Ω
CLn = 20 pF
Output
GND
Measurement
point
CL2
RL2
CL3
RL3
CL4
RL4
CL5
RL5
5
5
5
5



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