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UPD70732 Datasheet(PDF) 39 Page - NEC |
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UPD70732 Datasheet(HTML) 39 Page - NEC |
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39 / 66 page ![]() 39 µPD70732 Capacitance (TA = 25˚C, VDD = +5 V ± 10%) Parameter Symbol Test Conditions MIN. MAX. Unit Input capacitance CI fC = 1 MHz 15 pF I/O capacitance CIO 15 pF AC Characteristics (TA = –10 to +70˚C, VDD = +5V ± 10%) Clock Input Parameter Symbol Test µPD70732-16 µPD70732-20 µPD70732-25 Unit Conditions MIN. MAX. MIN. MAX. MIN. MAX. Clock cycle tCYK 62.5 50 40 ns Clock pulse high-level width tKKH 26 21 17 ns Clock pulse low-level width tKKL 26 21 17 ns Clock rise time tKR 54 3 ns Clock fall time tKF 54 3 ns Reset Parameter Symbol Test µPD70732-16 µPD70732-20 µPD70732-25 Unit Conditions MIN. MAX. MIN. MAX. MIN. MAX. RESET hold time (from VDD VALID) tHVR 1000 + 1000 + 1000 + ns 20 tCYKR 20 tCYKR 20 tCYKR Clock cycle (at reset) tCYKR 62.5 1000 50 1000 40 1000 ns Clock high-level time (at reset) tKKHR 26 21 17 ns Clock low-level time (at reset) tKKLR 26 21 17 ns RESET setup time (to CLK ↓, active) tSRKF 10 10 10 ns RESET setup time (to CLK ↓, inactive) tSRKR 10 10 10 ns RESET hold time (from CLK ↓)tHKR 10 10 10 ns RESET pulse low-level width (to CLK ↓) tWRL 20 tCYKR 20 tCYKR 20 tCYKR ns |
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