AN4104

DMA controller description

Doc ID 023131 Rev 1

3/13

1

DMA controller description

Direct memory access (DMA) is used in order to provide high-speed data transfer

betweenperipherals and memory as well as memory to memory. Data can be quickly moved

by DMA without any CPU actions. This keeps CPU resources free for other operations.

The DMA allows data transfers to take place in the background, without the intervention of

the Cortex-M0 processor. During this operation, the main processor can execute other tasks

and it is only interrupted when a whole data block is available for processing. Large amounts

of data can be transferred with no major impact on the system performance.

The DMA is mainly used to implement central data buffer storage (usually in system SRAM)

for different peripheral modules. This solution is less expensive in terms of silicon and power

consumption compared to a distributed solution where each peripheral needs to implement

its own local data storage.

Depending on the sales type used, one or two DMA controllers are implemented

.

The STM32F0xx DMA controller has 5 channels for DMA1 in total, each dedicated to

manage memory access requests from one or more peripherals. It has an arbiter for

handling the priority between DMA requests.

1.1

DMA Overview

The DMA(s) offer(s):

●

independently configurable channels (requests)

●

Each channels are connected to dedicated hardware DMA requests, software trigger is

also supported on each channel

●

Priorities between requests from channels of one DMA are software programmable (4

levels: very high, high, medium, low) or hardware in case of equality (request 1 has

priority over request 2, etc.)

●

Independent source and destination transfer size (byte, half word, word), emulating

packing and unpacking. The source and the address must have the same data size (to

be aligned on the data size).

●

Support for circular buffer management

●

3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)

logically ORed together in a single interrupt request for each channel

●

Memory-to-memory transfer

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Peripheral-to-memory and memory-to-peripheral as well as peripheral-to-peripheral

transfers

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Access to Flash, SRAM, APB and AHB peripherals as source and destination

●

Programmable number of data to be transferred: up to 65536

The DMA aims to offer a relatively large data buffer to all peripherals. This buffer is usually

located in system SRAM.

Each channel is assigned to a unique peripheral (data channel) at a given time. Peripherals

connected to the same DMA channel (CH1 to CH5 in Table 1 for STM32F0xx devices)

cannot be used simultaneously with active DMA (DMA function active in the peripheral

register).