DMA controller description

AN4104

4/13

Doc ID 023131 Rev 1

The different peripherals supporting DMA transfers in STM32F0xx devices are shown in

Table 1.

Note:

For more details,refer to RM0091 DMA section for STM32F0xx devices.

1.2

DMA Data managing

The DMA controller performs direct memory transfer by sharing the system bus with the

Cortex-M0 core. When the CPU and DMA are targeting the same destination (memory or

peripheral) the DMA request may stop the CPU access to the system bus for several bus

cycles. The bus matrix implements round-robin scheduling, thus ensuring at least half of the

system bus bandwidth (both to memory and peripheral) for the CPU.

Table 1.

Peripherals served by DMA1 and channel allocation

Peripherals

CH1

CH2

CH3

CH4

CH5

ADC

ADC1

ADC1

ADC1

SPI

SPI1

SPI1_RX

SPI1_TX

SPI2

SPI2_RX

SPI2_TX

USART

USART1

USART1_

TX

USART1_RX

USART1_

TX

USART1_RX

USART2

USART2_

TX

USART2_RX

I2C1_TX

I2C1_RX

I2C2_TX

I2C2_RX

TIM

TIM1

TIM1_CH1

TIM1_CH2

TIM1_CH4

TIM1_TRIG

TIM1_COM

TIM1_UP

TIM1_CH3

TIM2

TIM2_CH3

TIM2_UP

TIM2_CH2

TIM2_CH4

TIM2_CH1

TIM3

TIM3_CH3

TIM3_CH4

TIM3_UP

TIM3_CH1

TIM3_TRIG

TIM6/DAC

TIM6_UP

DAC

TIM15

TIM15_CH1

TIM15_UP

TIM15_TRIG

TIM15_COM

TIM16

TIM16_CH1

TIM16_UP

TIM16_CH1

TIM16_UP

TIM17

TIM17_CH1

TIM17_UP

TIM17_CH1

TIM17_UP